About me

I’m a fourth-year Ph.D. student at the Efficient Computing Lab in the Department of Computer Science & Engineering at POSTECH, advised by Prof. Eunhyeok Park. Before joining POSTECH, I completed my B.S. in the Department of Computer Science & Engineering at Kyung Hee University.

I’m currently focusing on Efficient AI, particularly in enhancing Memory Efficiency and Computation Acceleration during training and inference of various models (Vision, LLM, Physical AI, etc.) via Quantization and Low-rank Approximation.

Research Keywords

  • Low-Precision Training (A01, A02, C03, P01, P05)
  • Low-Precision Inference (C01, C02, P02)
  • KV Cache Compression via Low-rank Approximation (P04, PT01)
  • Parameter Efficient Fine-tuning of LLMs (P03)
  • HW–SW Co-design via Kernel Optimization (P01, P02, P04, P05)

News

Publications

Patents

  • [PT01] Power Iteration Method Based on Hadamard PCA and KV Cache Compression Methodology Using the Same
    Seonggon Kim, Taehyeon Kim, Eunhyeok Park
    Korean Patent Application No. 10-2025-0189902, filed Dec. 03, 2025.

Projects

  • [P05] Low-Precision Training on AMD GPU architecture, Nov. 2025 - May 2026
    Advanced Micro Devices
    • Conducted research on Low-Precision (MXFP4) Training on the AMD CDNA4 architecture.
    • Implemented ROCm kernel for training acceleration.
    • Achieved 3.6X memory compression, 1.46X acceleration over BF16.
    • Published in A02.

  • [P04] Solutions for slow SVD approximation problem of KV Cache compression, Feb. 2025 - Present
    POSTECH
    • Conducted research on the slow SVD approximation problem during KV Cache compression.
    • Implemented CUDA kernel for SVD approximation acceleration.
    • Achieved 5.1X acceleration and 95% similarity with exact SVD operation.
    • Filed as a Korean patent application PT01.
    • This work is currently under review.

  • [P03] Solutions for misaligned weight initialization problem of LoRA finetuning, Jun. 2025 - Present
    POSTECH
    • Conducted research on Effective LoRA weight initialization.
    • Achieved 99% accuracy of full fine-tuning with only rank 16.
    • This work is currently under review.

  • [P02] GEMV Accelerator for LLM inference on Intel Gaudi-2, Jun. 2024 - Jun. 2025
    Naver & Intel Joint Research Center
    • Conducted research on fast LLM inference on the Intel Gaudi-2 architecture.
    • Implemented custom GEMV kernel for Gaudi with TPC-C language.
    • Transplanted LUT Quantization from CUDA to Gaudi TPC.

  • [P01] Solutions for efficient training in limited GPU environments, Jun. 2023 - Present
    Ministry of Science and ICT of Korea
    • Conducted research on Low-Precision (INT4) Training in limited GPU environments.
    • Implemented CUDA kernel for training acceleration.
    • Achieved up to 75% memory savings and 2.6X acceleration over FP32.
    • Published in A01, C03.

Experience

  • Research Associate, Nov. 2025 - May 2026
    Advanced Micro Devices, Longmont, CO, USA

  • Software Engineer Intern, Jul. 2022 - Feb. 2023
    Spirent Communications, San Jose, CA, USA

  • Software Engineer Intern, Feb. 2022 - Jun. 2022
    Common Computer, Seoul, Korea

  • Research Intern, Mar. 2021 - Dec. 2021
    SI Analytics, Daejeon, Korea

Awards & Honors

  • Qualcomm Innovation Fellowship Korea, Winner, Oct. 2025

  • BK21 Outstanding Graduate Student International Training Scholarship, Recipient, Oct. 2025

  • CVPR 2021 EarthVision Workshop, Land Cover Classification Challenge, 5th Prize, Jun. 2021

Education

  • M.S./Ph.D. in Computer Science and Engineering, POSTECH
    Sep. 2023 - Present

  • B.S. in Computer Science and Engineering, Kyung Hee University
    Mar. 2017 - Aug. 2023

Teaching Experience

  • Teaching Assistant, Sep. 2026 - Dec. 2026
    CSED342: Artificial Intelligence, POSTECH

  • Teaching Assistant, Mar. 2025 - Jun. 2025
    CSED311: Computer Architecture, POSTECH

Academic Service

  • Reviewer, 2026
    Conference on Neural Information Processing Systems (NeurIPS 2026)